In prior art arrangement of this type (FIG. 1), switches (211, 212) are connected to power supply line (255). The switching is controlled by for example a modulator circuit (11) that encodes digital audio information into a suitable modulated control signal (e.g. Pulse width modulation (PWM)). The power switches transfer energy from the power supply line to the speaker load 200 and the modulation scheme is arranged such that the encoded audio waveform is reconstructed at the load.
Such a switching output stage may be organized as an Hbridge. For example Hbridge (22) has four power switches driving the load in a Bridge Tied Load (BTL). An Hbridge can be viewed as two half bridges (21) driving each side of the load (200). A Half bridge consists of 2 power switches (211,212)—typically MOSFET devices—in a “totem pole” output stage configuration, i.e. a high side switch (211) can connect the load to the positive supply and the other low side switch (212) can connect the load to the negative (or ground) line. Normally, only one of the switches in a half bridge (21) should be on at a time (i.e. break before make).
The half bridge switch devices (211, 212) are each controlled by gate drive circuits (231, 232) that turn the switches on and off in response to a PWM signal (124) from the PWM modulator (11). A PWM modulator arrangement is described in European Patent Application 0890221. Normally, there is also other circuitry in the signal path from the PWM signal (124) to the gate drive (231,232) inputs. A switching amplifier can consist of 1, 2 or even more half bridges connected in different ways to deliver power to the load. In the following analysis, one single half bridge (21) is considered; however, the same principles can be applied to amplifier systems with any number of half bridges.
Dead-time (also called blanking time) is the term used for the time gap in connection with the break-before make operation of a half bridge such as output stage (21). In such output stages, there are two power switches (211,212) forming a series connection from power supply line PVDD (255) to ground line (256). The dead time is defined as the period of time from one of the power switches (211, 212) opening to the other closing.
Any overlap in the on-state for the switches will result in shoot through, i.e. a shorting of the power supply, which is undesirable for potentially deleterious effects upon reliability and power consumption. When shoot through happens, the dead time is defined as being negative.
In a switching class D amplifier, the performance is very much dependent on the timing related to the switching of the output stage. Ideally, the dead time should be zero for all switching transitions, giving both high performance and minimum power consumption at the same time.
When there is a positive dead time, the output waveform (257) of the half bridge (21) is not itself controlled by the bridge, since for example the high side transistor is driven off while the low side transistor is not yet on, but instead depends upon the load current. It is this contribution to the behavior of the output waveform by the external load that gives rise to distortion. For instance, if the load current is from the half bridge the ground, then the low to high transition of the output waveform (257) will be delayed until the high side switch (211) turns on, whereas if the load current direction is opposite, the low-high transition happens sooner when the low side switch (212) turns off. This causes the output waveform to be modulated in a non-linear way as function of the load current and can be seen in the example shown in FIG. 2 wherein trace 20 shows the switching control signal. In response to this signal, low side turn off occurs first after a period 21 is represented by trace 22. The high side turn on occurs later after a period 23 as represented by trace 24. In this example, dead time is represented by .t.
Both theoretical analysis and the experimental results of the present inventors have shown a strong negative impact on amplifier THD performance as the dead time increases. It seems that this relationship is substantially a square-law, apparently each doubling of the dead time results in 4 times more THD. It has been found that, the dead time must be controlled to better than 10 ns for each half bridge in order to get around 0.1% THD and even better timing control is needed for better performance than that, typically 0.05% being the target for audiophile high fidelity applications. This means that timing control of each switch must be better than 5 ns (DTA) since the dead time is the timing difference between turn on (DTA) and off (DTB) of the upper and lower switch in a Half bridge, for example.
It is known that the performance (THD) can be improved by load control or compensation such as by adding capacitive snubber circuitry to the outputs of the half bridge/Hbridge. In such an arrangement, an example of which is described in European Patent Application 1086526, the snubber acts to reduce the rate of change in output waveform (257) and thereby reduce the non-linear effect of the dead time. However, such a snubber can add a significant charge/discharge power loss that is proportional to the switching frequency:P=U2*C*Fs
An improved snubber, described as a TT-snubber, is also described in EP 1086526 and with such a snubber (25)(FIG. 1), an output stage can sustain moderate shoot through (negative dead time) with less impact on performance and power consumption, however shoot through remains generally undesirable for the stated reasons even with such reduced susceptibility.
Clearly, an ideal implementation of a PWM amplifier would have zero deadtime; since this is not realisable, a good design will have as little deadtime as possible. Unfortunately, deadtime varies with many factors both operating and manufacturing and designing for optimum deadtime with all things considered is a daunting compromise. For this reason, numerous compensating arrangements have been applied to half bridge output stages. They fall principally into two groups: those which seek to compensate a characteristic of the bridge or the bridge devices directly (such as speed up circuits) and those which split the drive signal to the bridge halves and then seek to introduce compensating imbalance to the split drive signals.
However achieved, the goal of the added timing compensation circuitry is to make sure that the output stage operates as close to zero dead time as possible and, furthermore, to ensure that the Hbridge or half bridge responds with the same delay for low to high as for high to low transitions.
If two or more half bridge devices are to be connected in parallel operation (e.g. in order to get more power output), the requirement is furthermore that the timing of the output stages is matched within reasonable limits.
There are yet more issues which confront the designer of an integrated half bridge. For a deadtime control circuit which is a fixed or integrated design, semi-conductor manufacturing process variations set a lower limit on how well the control can work. The power processes needed to design monolithic Hbridges have typically bigger device sizes than processes for logic gate devices, leading to overall bigger switching delays for such devices. Their large size also gives a relatively big production spread in timing data and a relatively big temperature coefficient.
The big spread in timing properties gives yield problems when a certain THD performance level is required since for a reasonable yield a relatively poor performance device must be assumed in the design phase.
Furthermore, the timing of any circuitry is generally temperature dependent. This means that the performance will change over the temperature range, similarly affecting yield. Another approach is to try to control the device timing by changing the design of the circuitry. This will often involve adding more die area and thereby increase the cost. For example, one can add more complex compensating circuitry that reduces the effective temperature coefficient of the timing parameters.
In attempting to control deadtime, various arrangements which change the timing (i.e. the propagation delays) for the individual high side and low side control signals inside a half bridge have been used, e.g. circuitry that adds increments to the timing for the high side and low side controls. Since the propagation delays can only be made longer, i.e. delays which are device or process driven cannot be reduced, typically a circuit is used that can add more propagation delay at Low to high (LH) than for High to Low (LH), since this will add to the resulting dead time.
Typically, the control of the high and low sides has been separated and a circuit has been inserted in the logic path from the control input (e.g. the PWM input 124) to the high side and low side switch control signals. Such an arrangement can add dead-time by delaying the turn on more than the turn off.
The circuits/principles known to date are:                Diode plus resistor in parallel in gate drive for output mosfet switches. The turn on is slowed down by the series resistor, while the turn off is fast through the diode. This is a straight forward example of a trade off between lower distortion (performance) and added deadtime (power).        Open drain/collector logic output connected to a pull up current source/resistor with a capacitor to ground. This adds more delay at the LH transmition.        Addition of a logic network, e.g. a logical ‘AND’ between the control signal (which controls HL) and a delayed version of the same signal to provide a delay LH control.        Delay introduced by digital clock edges using e.g. LH control signal transmitted via D-type flip-flops to add a clocking delay.        Sensing of half bridge output node voltages to block the low side MOSFET switch from turning on until the output node voltage goes low.        Sensing of the low side power MOSFET switch gate signal in order to block the high side MOSFET from turning on until low side has turned off. These latter two cases are examples of how the power supply can be constructed to reduce distortion.        
Drawbacks of the prior art approaches include the following:                They add the same additional delays for both high side and the low side path.        Dead time can never be reduced, since the solutions themselves add to the deadtime.        Some circuits are fixed and therefore raise yield issues as described above.        For other circuits, individual trimming is needed to compensate component tolerances and process variation, which implies expensive adjustment on test procedures or selection; more likely the circuit will be designed to a compromise and a yield or a performance degradation tolerated.        Designed for Power Supply purposes and not for meeting amplifier THD performance constraints. In switch Mode Power supplies, one normally seeks to have a high dead time to avoid shoot through, while THD is not a concern. Most circuits have been developed for power supplies and not for amplifiers where THD is a big concern.        
As stated above, in principle, only one logic signal is needed to control a half bridge, i.e. to bring it to either a high state (high side on and low side off) or a low state (low side on and high side off).
A half bridge may be characterized by 4 timing constants measured from a single logic control input transition (e.g. the PWM signal 124 transition) to when the actual switching in the output stage takes place. The constant are determined by device parameters and may be identified as:
(1) TPD(high side turn on)
(2) TPD(high side turn off)
(3) TPD(low side turn on)
(4) TPD(low side turn off)
The dead time for the high to low (HL) transition is expressed as:Tdead(HL)=TPD(low side turn on)−TPD(high side turn off)
Similarly, the dead time at the low to high transition (LH) is:Tdead(LH)=TPD(high side turn on)−TPD(low side turn off)
One common problem is that if there is a general difference in delay between the high side and the low side paths, then this timing delta will add to the dead time at one transition and subtract in the other transition. This creates a difference in the dead-times of LH and HL of twice the delay delta. A consequence of this can be that one transition (e.g. low to high) will exhibit shoot trough while the other transition (e.g. high to low) has a long dead time. This gives the very undesirable combination of bad performance and high power consumption.
However, even if the dead time is zero at each transition (which would be the ideal case), there can still be errors due to the timing differences between the LH and HL transitions. Such timing differences will effectively change the pulse width of an incoming PWM control signal, i.e. the pulse width of an incoming control pulse will not be replicated at the power output, giving rise to duty cycle distortion, which will add to the dead time distortion of the non-ideal case.
Postulating again an ideal case means that we have the same delay for turn-on of the high side as for the low side. Together with the requirements for zero dead time, we now have 4 unknowns and 3 constraints (equations 1–3):TPD(high side turn on)=TPD(low side turn on)  1.Tdead(HL)=TPD(low side turn on)−TPD(high side turn off)=0  2.Tdead(LH)=TPD(high side turn on)−TPD(low side turn off)=0  3.
There is 1 degree of freedom for this system of equations, and one may therefore choose the total delay freely (e.g. TPD (high side turn on)).
The consequence if the TPD (high side turn on)=TPD(low side turn on) constraint is not met in practice is that the resulting pulse width would be different from the pulse width of the incoming control signal.
The effect of this pulse width error is not analyzed here in detail however it is noted that it would constitute a fixed pulse width error, so for static DC signals, there would be only a fixed DC offset error and not non-linear distortion.
For an H-bridge arrangement another issue is that the pulse width error causes a DC offset if the timing delays of the two half bridges are different, even if the two half bridges in every other respect are matched.